Recently, in a semiconductor integrated circuit (LSI: Large Scale Integrated Circuit), the amount of the circuits integrated in one chip has been increased and the performance of the circuits has also been improved along with the further miniaturization in the semiconductor manufacturing processes. However, when chips are sealed in a package and the package is mounted on a board, communication performance is degraded due to the long communication distance between the chips, and the communication performance cannot catch up with the performance improvement in the chips. Moreover, due to the influence of, for example, miniaturization limit and increase in the cost to use most-advanced processes, the conventional performance improvement by the integration onto one chip will not always be the most optimum solution in the future.
As a technique for improving the performance between chips, Patent Document 1 discloses the technique of three-dimensionally stacking a plurality of chips and connecting the respective chips by using through silicon vias to carry out inter-chip communication. Also, Patent Document 2 introduces the technique of finding out short-circuit fault of through electrodes used for signals.